Added additional Structs
This commit is contained in:
mrumel
parent
fbe920e529
commit
4851bfc50a
1 changed files with 591 additions and 6 deletions
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@ -1,5 +1,7 @@
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import ctypes
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from enum import Enum
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uint8_t = ctypes.c_uint8
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uint16_t = ctypes.c_uint16
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uint32_t = ctypes.c_uint32
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import spidev
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@ -41,6 +43,8 @@ class TCAN4550:
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self.TCANDataTiming.DataTqBeforeSamplePoint = 15;
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self.TCANDataTiming.DataTqAfterSamplePoint = 5;
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def TCAN_clearSPIerr(self) -> None:
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@ -69,14 +73,595 @@ class TCAN4550:
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class TCAN4x5x_GFC_NO_MATCH_BEHAVIOR(Enum): #No Comments provided in original file
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TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 = 0,
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TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 = 1,
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TCAN4x5x_GFC_REJECT = 2
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class TCAN4x5x_MRAM_Element_Data_Size(Enum):
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# 8 bytes of data payload
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MRAM_8_Byte_Data = 0,
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# 12 bytes of data payload
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MRAM_12_Byte_Data = 0x1,
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# 16 bytes of data payload
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MRAM_16_Byte_Data = 0x2,
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# 20 bytes of data payload
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MRAM_20_Byte_Data = 0x3,
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# 24 bytes of data payload
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MRAM_24_Byte_Data = 0x4,
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# 32 bytes of data payload
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MRAM_32_Byte_Data = 0x5,
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# 48 bytes of data payload
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MRAM_48_Byte_Data = 0x6,
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# 64 bytes of data payload
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MRAM_64_Byte_Data = 0x7
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class TCAN4x5x_MCAN_Data_Timing_Simple(ctypes.Structure):
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_fields_ = [
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# Prescaler value, interpreted as 1:x
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# Valid range is: 1 to 32
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("DataBitRatePrescaler", uint8_t, 6),
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# DTQBSP: Number of time quanta before sample point
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# Valid values are: 2 to 33
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("DataTqBeforeSamplePoint", uint8_t, 6),
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# DTQASP: Number of time quanta after sample point
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# Valid values are: 1 to 16
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("DataTqAfterSamplePoint", uint8_t, 5)
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]
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class TCAN4x5x_MCAN_Data_Timing_Raw(ctypes.Structure):
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_fields_= [
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# DBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field + 1
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# Valid range is: 0 to 31
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("DataBitRatePrescaler", uint8_t, 5),
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# DTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value in this field + 1
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# Valid values are: 0 to 31
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("DataTimeSeg1andProp", uint8_t, 5),
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# DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 15
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("DataTimeSeg2", uint8_t, 4),
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# DSJW: Data Resynchronization jump width. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 15
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("DataSyncJumpWidth", uint8_t, 4),
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# TDCO: Transmitter delay compensation offset
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# Valid values are 0 to 127 mtq
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("TDCOffset", uint8_t, 7),
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# TDCFilter: Transmitter delay compensation Filter Window Length
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# Valid values are 0 to 127 mtq
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("TDCFilter", uint8_t, 7)
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]
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class TCAN4x5x_MCAN_Nominal_Timing_Simple(ctypes.Structure):
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_fields_ = [
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# NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x
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# Valid range is: 1 to 512
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("NominalBitRatePrescaler", uint16_t, 10),
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# NTQBSP: The total number of time quanta prior to sample point
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# Valid values are: 2 to 257
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("NominalTqBeforeSamplePoint", uint16_t, 9),
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# NTQASP: The total number of time quanta after the sample point
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# Valid values are: 2 to 128
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("NominalTqAfterSamplePoint", uint8_t, 8)
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]
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class TCAN4x5x_MCAN_Nominal_Timing_Raw(ctypes.Structure):
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_fields_ = [
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# NBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field + 1
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# Valid range is: 0 to 511
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("NominalBitRatePrescaler", uint16_t, 9),
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# NTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 255
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("NominalTimeSeg1andProp", uint8_t, 8),
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# NTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 127
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("NominalTimeSeg2", uint8_t, 7),
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# NSJW: Nominal time Resynchronization jump width. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 127
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("NominalSyncJumpWidth", uint8_t, 7)
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]
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class TCAN4x5x_MRAM_Config(ctypes.Structure):
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_fields_ = [
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# ************************
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# Filter Elements *
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# ************************
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# Standard ID Number of Filter Elements: The number of 11-bit filters the user would like
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# Valid range is: 0 to 128
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("SIDNumElements", uint8_t, 8),
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# Extended ID Number of Filter Elements: The number of 29-bit filters the user would like
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# Valid range is: 0 to 64
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("XIDNumElements", uint8_t, 7),
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# /************************
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# RX FIFO Elements *
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# ************************/
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# RX FIFO 0 number of elements: The number of elements for the RX FIFO 0
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# Valid range is: 0 to 64
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("Rx0NumElements", uint8_t, 7),
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# RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
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("Rx0ElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
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# RX FIFO 1 number of elements: The number of elements for the RX FIFO 1
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# Valid range is: 0 to 64
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("Rx1NumElements", uint8_t, 7),
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# RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
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("Rx1ElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
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# RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO)
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# Valid range is: 0 to 64
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("RxBufNumElements", uint8_t, 7),
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# RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO
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("RxBufElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
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# /************************
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#TX Buffer Elements *
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# ************************/
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# TX Event FIFO number of elements: The number of elements for the TX Event FIFO
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# Valid range is: 0 to 32
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("TxEventFIFONumElements", uint8_t, 6),
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# TX Buffers number of elements: The number of elements for the TX Buffers
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# Valid range is: 0 to 32
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("TxBufferNumElements", uint8_t, 6),
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# TX Buffers element size: The number of bytes for the TX Buffers (data payload)
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("TxBufferElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3)
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]
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class TCAN4x5x_MCAN_Interrupt_Enable_bits(ctypes.Structure):
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_fields_ = [
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# IE[0] RF0NE: Rx FIFO 0 new message
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("RF0NE", uint8_t, 1),
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# IE[1] RF0WE: Rx FIFO 0 watermark reached
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("RF0WE", uint8_t, 1),
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# IE[2] RF0FE: Rx FIFO 0 full
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("RF0FE", uint8_t, 1),
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# IE[3] RF0LE: Rx FIFO 0 message lost
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("RF0LE", uint8_t, 1),
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# IE[4] RF1NE: Rx FIFO 1 new message
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("RF1NE", uint8_t, 1),
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# IE[5] RF1WE: RX FIFO 1 watermark reached
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("RF1WE", uint8_t, 1),
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# IE[6] RF1FE: Rx FIFO 1 full
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("RF1FE", uint8_t, 1),
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# IE[7] RF1LE: Rx FIFO 1 message lost
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("RF1LE", uint8_t, 1),
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# IE[8] HPME: High priority message
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("HPME", uint8_t, 1),
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# IE[9] TCE: Transmission completed
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("TCE", uint8_t, 1),
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# IE[10] TCFE: Transmission cancellation finished
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("TCFE", uint8_t, 1),
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# IE[11] TFEE: Tx FIFO Empty
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("TFEE", uint8_t, 1),
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# IE[12] TEFNE: Tx Event FIFO new entry
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("TEFNE", uint8_t, 1),
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# IE[13] TEFWE: Tx Event FIFO watermark reached
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("TEFWE", uint8_t, 1),
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# IE[14] TEFFE: Tx Event FIFO full
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("TEFFE", uint8_t, 1),
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# IE[15] TEFLE: Tx Event FIFO element lost
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("TEFLE", uint8_t, 1),
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# IE[16] TSWE: Timestamp wraparound
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("TSWE", uint8_t, 1),
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# IE[17] MRAFE: Message RAM access failure
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("MRAFE", uint8_t, 1),
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# IE[18] TOOE: Time out occured
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("TOOE", uint8_t, 1),
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# IE[19] DRXE: Message stored to dedicated RX buffer
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("DRXE", uint8_t, 1),
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# IE[20] BECE: MRAM Bit error corrected
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("BECE", uint8_t, 1),
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# IE[21] BEUE: MRAM Bit error uncorrected
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("BEUE", uint8_t, 1),
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# IE[22] ELOE: Error logging overflow
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("ELOE", uint8_t, 1),
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# IE[23] EPE: Error_passive status changed
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("EPE", uint8_t, 1),
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# IE[24] EWE: Error_warning status changed
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("EWE", uint8_t, 1),
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# IE[25] BOE: Bus_off status changed
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("BOE", uint8_t, 1),
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# IE[26] WDIE: MRAM Watchdog Interrupt
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("WDIE", uint8_t, 1),
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# IE[27] PEAE Protocol Error in arbitration phase (nominal bit time used)
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("PEAE", uint8_t, 1),
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# IE[28] PEDE: Protocol error in data phase (data bit time is used)
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("PEDE", uint8_t, 1),
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# IE[29] ARAE: Access to reserved address
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("ARAE", uint8_t, 1),
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# IE[30:31] Reserved, not writable
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("reserved", uint8_t, 2)
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]
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class TCAN4x5x_MCAN_Interrupt_Enable(ctypes.Union):
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_fields_= [("b", TCAN4x5x_MCAN_Interrupt_Enable_bits),
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("word", uint32_t)]
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class TCAN4x5x_MCAN_Interrupts_bits(ctypes.Structure):
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_fields_ = [
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# IR[0] RF0N: Rx FIFO 0 new message
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("RF0N", uint8_t, 1),
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# IR[1] RF0W: Rx FIFO 0 watermark reached
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("RF0W", uint8_t, 1),
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# IR[2] RF0F: Rx FIFO 0 full
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("RF0F", uint8_t, 1),
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# IR[3] RF0L: Rx FIFO 0 message lost
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("RF0L", uint8_t, 1),
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# IR[4] RF1N: Rx FIFO 1 new message
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("RF1N", uint8_t, 1),
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# IR[5] RF1W: RX FIFO 1 watermark reached
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("RF1W", uint8_t, 1),
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# IR[6] RF1F: Rx FIFO 1 full
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("RF1F", uint8_t, 1),
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# IR[7] RF1L: Rx FIFO 1 message lost
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("RF1L", uint8_t, 1),
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# IR[8] HPM: High priority message
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("HPM", uint8_t, 1),
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# IR[9] TC: Transmission completed
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("TC", uint8_t, 1),
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# IR[10] TCF: Transmission cancellation finished
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("TCF", uint8_t, 1),
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# IR[11] TFE: Tx FIFO Empty
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("TFE", uint8_t, 1),
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# IR[12] TEFN: Tx Event FIFO new entry
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("TEFN", uint8_t, 1),
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# IR[13] TEFW: Tx Event FIFO water mark reached
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("TEFW", uint8_t, 1),
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# IR[14] TEFF: Tx Event FIFO full
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("TEFF", uint8_t, 1),
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# IR[15] TEFL: Tx Event FIFO element lost
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("TEFL", uint8_t, 1),
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# IR[16] TSW: Timestamp wrapped around
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("TSW", uint8_t, 1),
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# IR[17] MRAF: Message RAM access failure
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("MRAF", uint8_t, 1),
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# IR[18] TOO: Time out occurred
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("TOO", uint8_t, 1),
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# IR[19] DRX: Message stored to dedicated RX buffer
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("DRX", uint8_t, 1),
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# IR[20] BEC: MRAM Bit error corrected
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("BEC", uint8_t, 1),
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# IR[21] BEU: MRAM Bit error uncorrected
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("BEU", uint8_t, 1),
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# IR[22] ELO: Error logging overflow
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("ELO", uint8_t, 1),
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# IR[23] EP: Error_passive status changed
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("EP", uint8_t, 1),
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# IR[24] EW: Error_warning status changed
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("EW", uint8_t, 1),
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# IR[25] BO: Bus_off status changed
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("BO", uint8_t, 1),
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# IR[26] WDI: MRAM Watchdog Interrupt
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("WDI", uint8_t, 1),
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# IR[27] PEA Protocol Error in arbitration phase (nominal bit time used)
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("PEA", uint8_t, 1),
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# IR[28] PED: Protocol error in data phase (data bit time is used)
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("PED", uint8_t, 1),
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# IR[29] ARA: Access to reserved address
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("ARA", uint8_t, 1),
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# IR[30:31] Reserved, not writable
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("reserved", uint8_t, 1)
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]
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class TCAN4x5x_MCAN_Interrupts(ctypes.Union):
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_fields_ = [("b", TCAN4x5x_MCAN_Interrupts_bits),
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("words", uint32_t)]
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class TCAN4x5x_MCAN_RX_Header(ctypes.Structure):
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_fields_ = [
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# CAN ID received
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("ID", uint32_t, 29),
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# Remote Transmission Request flag
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("RTR", uint8_t, 1),
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# Extended Identifier flag
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("XTD", uint8_t, 1),
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# Error state indicator flag
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("ESI", uint8_t, 1),
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# Receive time stamp
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("RXTS", uint16_t, 16),
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# Data length code
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("DLC", uint8_t, 4),
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# Bit rate switch used flag
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("BRS", uint8_t, 1),
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# CAN FD Format flag
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("FDF", uint8_t, 1),
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# Reserved (0)
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("reserved", uint8_t, 2),
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# Filter index that this message matched
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("FIDX", uint8_t, 7),
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# Accepted non matching frame flag
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("ANMF", uint8_t, 1)
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]
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class TCAN4x5x_Device_Interrupts_bits(ctypes.Structure):
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_fields_ = {
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# DEV_IR[0] VTWD: Global Voltage, Temp, or Watchdog (if equipped) Interrupt
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("VTWD", uint8_t, 1),
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# DEV_IR[1] M_CAN_INT: There are MCAN interrupts pending
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("M_CAN_INT", uint8_t, 1),
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# DEV_IR[2] : Selective Wake Error (If equipped)
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("SWERR", uint8_t, 1),
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# DEV_IR[3] : SPI Error
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("SPIERR", uint8_t, 1),
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# DEV_IR[4] : CBF, CAN Bus Fault
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("CBF", uint8_t, 1),
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# DEV_IR[5] : CANERR, CAN Error
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("CANERR", uint8_t, 1),
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# DEV_IR[6] : WKRQ, Wake Request
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("WKRQ", uint8_t, 1),
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# DEV_IR[7] : GLOBALERR, Global Error. Is the OR output of all interrupts
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("GLOBALERR", uint8_t, 1),
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# DEV_IR[8] : CANDOM, Can bus stuck dominant
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("CANDOM", uint8_t, 1),
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# DEV_IR[9] : RESERVED
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("RESERVED", uint8_t, 1),
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# DEV_IR[10] : CANTO, CAN Timeout
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("CANTO", uint8_t, 1),
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# DEV_IR[11] : RESERVED
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("RESERVED2", uint8_t, 1),
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# DEV_IR[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
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("FRAME_OVF", uint8_t, 1),
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# DEV_IR[13] : WKERR, Wake Error
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("WKERR", uint8_t, 1),
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# DEV_IR[14] : LWU, Local Wake Up
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("LWU", uint8_t, 1),
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# DEV_IR[15] : CANINT, CAN Bus Wake Up Interrupt
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("CANINT", uint8_t, 1),
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# DEV_IR[16] : ECCERR, MRAM ECC Error
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||||
("ECCERR", uint8_t, 1),
|
||||
|
||||
# DEV_IR[17] : Reserved
|
||||
("RESERVED3", uint8_t, 1),
|
||||
|
||||
# DEV_IR[18] : WDTO, Watchdog Time Out
|
||||
("WDTO", uint8_t, 1),
|
||||
|
||||
# DEV_IR[19] : TSD, Thermal Shut Down
|
||||
("TSD", uint8_t, 1),
|
||||
|
||||
# DEV_IR[20] : PWRON, Power On Interrupt
|
||||
("PWRON", uint8_t, 1),
|
||||
|
||||
# DEV_IR[21] : UVIO, Undervoltage on UVIO
|
||||
("UVIO", uint8_t, 1),
|
||||
|
||||
# DEV_IR[22] : UVSUP, Undervoltage on VSUP and VCCOUT
|
||||
("UVSUP", uint8_t, 1),
|
||||
|
||||
# DEV_IR[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults
|
||||
("SMS", uint8_t, 1),
|
||||
|
||||
# DEV_IR[24] : CANBUSBAT, CAN Shorted to VBAT
|
||||
("CANBUSBAT", uint8_t, 1),
|
||||
|
||||
# DEV_IR[25] : CANBUSGND, CAN Shorted to GND
|
||||
("CANBUSGND", uint8_t, 1),
|
||||
|
||||
# DEV_IR[26] : CANBUSOPEN, CAN Open fault
|
||||
("CANBUSOPEN", uint8_t, 1),
|
||||
|
||||
# DEV_IR[27] : CANLGND, CANL GND
|
||||
("CANLGND", uint8_t, 1),
|
||||
|
||||
# DEV_IR[28] : CANHBAT, CANH to VBAT
|
||||
("CANHBAT", uint8_t, 1),
|
||||
|
||||
# DEV_IR[29] : CANHCANL, CANH and CANL shorted
|
||||
("CANHCANL", uint8_t, 1)
|
||||
|
||||
# DEV_IR[30] : CANBUSTERMOPEN, CAN Bus has termination point open
|
||||
("CANBUSTERMOPEN", uint8_t, 1)
|
||||
|
||||
# DEV_IR[31] : CANBUSNOM, CAN Bus is normal flag
|
||||
("CANBUSNORM", uint8_t, 1)
|
||||
}
|
||||
|
||||
class TCAN4x5x_Device_Interrupts(ctypes.Union):
|
||||
_fields_ = [("b", TCAN4x5x_Device_Interrupts_bits),
|
||||
("word", uint32_t)]
|
||||
|
||||
|
||||
class TCAN4x5x_MCAN_CCCR_Config_bits(ctypes.Structure):
|
||||
_fields_ = [
|
||||
# Reserved (0)
|
||||
("reserved", uint8_t, 2),
|
||||
|
||||
# ASM: Restricted Operation Mode. The device can only listen to CAN traffic and acknowledge, but not send anything.
|
||||
("ASM", uint8_t, 1),
|
||||
|
||||
# Reserved (0)
|
||||
("reserved2", uint8_t, 1),
|
||||
|
||||
# CSR: Clock stop request
|
||||
("CSR", uint8_t, 1),
|
||||
|
||||
# MON: Bus monitoring mode. The device may only listen to CAN traffic, and is not allowed to acknowledge or send error frames.
|
||||
("MON", uint8_t, 1),
|
||||
|
||||
# DAR: Disable automatic retransmission. If a transmission errors, gets a NACK, or loses arbitration, the MCAN controller will NOT try to transmit again
|
||||
("DAR", uint8_t, 1),
|
||||
|
||||
# TEST: MCAN Test mode enable
|
||||
("TEST", uint8_t, 1),
|
||||
|
||||
# FDOE: Can FD mode enabled, master enable for CAN FD support
|
||||
("FDOE", uint8_t, 1),
|
||||
|
||||
# BRSE: Bit rate switch enabled for can FD. Master enable for bit rate switching support
|
||||
("BRSE", uint8_t, 1),
|
||||
|
||||
# Reserved (0)
|
||||
("reserved3", uint8_t, 1),
|
||||
|
||||
# PXHD: Protocol exception handling disable
|
||||
# 0 = Protocol exception handling enabled [default]
|
||||
# 1 = protocol exception handling disabled
|
||||
("PXHD", uint8_t, 1),
|
||||
|
||||
# EFBI: Edge filtering during bus integration. 0 Disables this [default]
|
||||
("EFBI", uint8_t, 1),
|
||||
|
||||
# TXP: Transmit Pause Enable: Pause for 2 can bit times before next transmission
|
||||
("TXP", uint8_t, 1),
|
||||
|
||||
# NSIO: Non Iso Operation
|
||||
# 0: CAN FD frame format according to ISO 11898-1:2015 [default]
|
||||
# 1: CAN FD frame format according to Bosch CAN FD Spec v1
|
||||
("NISO", uint8_t, 1)
|
||||
]
|
||||
|
||||
class TCAN4x5x_MCAN_CCCR_Config(ctypes.Union):
|
||||
_fields_ = [("b", TCAN4x5x_MCAN_CCCR_Config_bits),
|
||||
("word", uint32_t)]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
class TCAN4x5x_MCAN_Global_Filter_Configuration_bits(ctypes.Structure):
|
||||
_fields_ = [
|
||||
# GFC[0] : Reject Remote Frames for Extended IDs
|
||||
("RRFE", uint8_t, 1)
|
||||
|
||||
# GFC[1] : Reject Remote Frames for Standard IDs
|
||||
("RRFS", uint8_t, 1),
|
||||
|
||||
# GFC[3:2] : Accept Non-matching Frames Extended
|
||||
# Valid values:
|
||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accept into RXFIFO0
|
||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 : Accept into RXFIFO1
|
||||
# TCAN4x5x_GFC_REJECT : Reject
|
||||
("ANFE", TCAN4x5x_GFC_NO_MATCH_BEHAVIOR, 2),
|
||||
|
||||
# GFC[5:4] : Accept Non-matching Frames Standard
|
||||
# Valid values:
|
||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accept into RXFIFO0
|
||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 : Accept into RXFIFO1
|
||||
# TCAN4x5x_GFC_REJECT : Reject
|
||||
("ANFS", TCAN4x5x_GFC_NO_MATCH_BEHAVIOR, 2),
|
||||
|
||||
# Reserved
|
||||
("reserved", uint32_t, 26)
|
||||
]
|
||||
class TCAN4x5x_MCAN_Global_Filter_Configuration(ctypes.Union):
|
||||
_fields_ = [("b", TCAN4x5x_MCAN_Global_Filter_Configuration_bits),
|
||||
("word", uint32_t)]
|
||||
|
||||
|
||||
class TCAN4550_device_interrupt_enable_bits(ctypes.BigEndianStructure):
|
||||
class TCAN4x5x_device_interrupt_enable_bits(ctypes.BigEndianStructure):
|
||||
_fields_ = [
|
||||
# @brief DEV_IE[0:7] : RESERVED
|
||||
("RESERVED1", uint8_t , 8),
|
||||
|
|
@ -154,6 +739,6 @@ class TCAN4550_device_interrupt_enable_bits(ctypes.BigEndianStructure):
|
|||
("CANBUSNORMEN", uint8_t , 1)
|
||||
]
|
||||
|
||||
class TCAN4550_device_interrupt_enable(ctypes.Union):
|
||||
_fields_ = [("b", TCAN4550_device_interrupt_enable_bits),
|
||||
class TCAN4x5x_device_interrupt_enable(ctypes.Union):
|
||||
_fields_ = [("b", TCAN4x5x_device_interrupt_enable_bits),
|
||||
("word", uint32_t)]
|
||||
Loading…
Add table
Add a link
Reference in a new issue