Continue work on Device config
This commit is contained in:
parent
4851bfc50a
commit
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2 changed files with 273 additions and 222 deletions
3
.gitignore
vendored
3
.gitignore
vendored
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@ -5,4 +5,5 @@ build
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dist
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dist
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__pycache__
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__pycache__
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*.egg-info
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*.egg-info
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_build
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_build
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.idea
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@ -1,14 +1,15 @@
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import ctypes
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import ctypes
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from enum import Enum
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from enum import Enum
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uint8_t = ctypes.c_uint8
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uint8_t = ctypes.c_uint8
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uint16_t = ctypes.c_uint16
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uint16_t = ctypes.c_uint16
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uint32_t = ctypes.c_uint32
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uint32_t = ctypes.c_uint32
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import spidev
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import spidev
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class TCAN4550:
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class TCAN4550:
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def __init__(self, bus:int, device:int) -> None:
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def __init__(self, bus: int, device: int) -> None:
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# SPI initialization
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# SPI initialization
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self.spi = spidev.SpiDev(bus, device)
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self.spi = spidev.SpiDev(bus, device)
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self.spi.max_speed_hz = 2000000
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self.spi.max_speed_hz = 2000000
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@ -16,68 +17,104 @@ class TCAN4550:
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self.spi.mode = 0b00
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self.spi.mode = 0b00
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self.spi.cshigh = True
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self.spi.cshigh = True
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# TCAN device initialization
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# TCAN device initialization
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# Begin by clearing any potential SPI errors
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# Begin by clearing any potential SPI errors
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self.TCAN_clearSPIerr()
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self.TCAN_clearSPIerr()
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self.dev_ie = TCAN4550_device_interrupt_enable()
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self.dev_ie = TCAN4x5x_device_interrupt_enable()
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self.dev_ie = 0x0 # Initialize to 0 to all bits are set to 0.
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self.dev_ie = 0x0 # Initialize to 0 to all bits are set to 0.
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self.TCAN_configure_interrupt_enable(self.dev_ie) # Disable all non-MCAN related interrupts for simplicity
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self.TCAN_configure_interrupt_enable(self.dev_ie) # Disable all non-MCAN related interrupts for simplicity
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self.dev_ir = TCAN4550_device_interrupt()
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self.dev_ir = TCAN4x5x_Device_Interrupts()
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self.dev.ir = 0x0 # Setup a new MCAN IR object for easy interrupt checking
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self.dev_ir = 0x0 # Setup a new MCAN IR object for easy interrupt checking
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self.TCAN_read_interrupts(self.dev_ir) # Request that the struct be updated with current DEVICE (not MCAN) interrupt values
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self.TCAN_read_interrupts(
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self.dev_ir) # Request that the struct be updated with current DEVICE (not MCAN) interrupt values
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if self.dev_ir.b.PWRON:
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self.TCAN4x5x_Device_ClearInterrupts(self.dev_ir)
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# Configure the CAN bus speeds
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# Configure the CAN bus speeds
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self.TCANNomTiming = TCAN4550_MCAN_nominal_timing_simple() # 500k arbitration with a 40 MHz crystal ((40E6 / 2) / (32 + 8) = 500E3)
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self.TCANNomTiming = TCAN4x5x_MCAN_Nominal_Timing_Simple() # 500k arbitration with a 40 MHz crystal ((40E6 / 2) / (32 + 8) = 500E3)
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self.TCANNomTiming = 0x0
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self.TCANNomTiming = 0x0
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self.TCANNomTiming.NominalBitRatePrescaler = 2
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self.TCANNomTiming.NominalBitRatePrescaler = 2
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self.TCANNomTiming.NominalTqBeforeSamplePoint = 32
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self.TCANNomTiming.NominalTqBeforeSamplePoint = 32
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self.TCANNomTiming.NominalTqAfterSamplePoint = 8
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self.TCANNomTiming.NominalTqAfterSamplePoint = 8
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self.TCANDataTiming = TCAN4550_MCAN_nominal_timing_simple() # 2 Mbps CAN FD with a 40 MHz crystal (40E6 / (15 + 5) = 2E6)
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self.TCANDataTiming = TCAN4x5x_MCAN_Nominal_Timing_Simple() # 2 Mbps CAN FD with a 40 MHz crystal (40E6 / (15 + 5) = 2E6)
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self.TCANDataTiming = 0x0
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self.TCANDataTiming = 0x0
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self.TCANDataTiming.DataBitRatePrescaler = 1;
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self.TCANDataTiming.DataBitRatePrescaler = 1
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self.TCANDataTiming.DataTqBeforeSamplePoint = 15;
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self.TCANDataTiming.DataTqBeforeSamplePoint = 15
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self.TCANDataTiming.DataTqAfterSamplePoint = 5;
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self.TCANDataTiming.DataTqAfterSamplePoint = 5
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# Configure the MCAN core settings
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self.cccrConfig = TCAN4x5x_MCAN_CCCR_Config()
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self.cccrConfig = 0x0 # Remember to initialize to 0, or you'll get random garbage!
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self.cccrConfig.b.FDOE = 1 # CAN FD mode enable
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self.cccrConfig.b.BRSE = 1 # CAN FD Bit rate switch enable
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# Configure the default CAN packet filtering settings
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self.gfc = TCAN4x5x_MCAN_Global_Filter_Configuration()
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self.gfc.b.RRFE = 1 # Reject remote frames (TCAN4x5x doesn't support this)
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self.gfc.b.RRFS = 1 # Reject remote frames (TCAN4x5x doesn't support this)
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self.gfc.b.ANFE = TCAN4x5x_GFC_NO_MATCH_BEHAVIOR.TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0.value # Default behavior if incoming message doesn't match a filter is to accept into RXFIO0 for extended ID messages (29 bit IDs)
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self.gfc.b.ANFS = TCAN4x5x_GFC_NO_MATCH_BEHAVIOR.TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0.value # Default behavior if incoming message doesn't match a filter is to accept into RXFIO0 for standard ID messages (11 bit IDs)
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'''
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In the next configuration block, we will set the MCAN core up to have:
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- 1 SID filter element
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- 1 XID Filter element
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- 5 RX FIFO 0 elements
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- RX FIFO 0 supports data payloads up to 64 bytes
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- RX FIFO 1 and RX Buffer will not have any elements, but we still set their data payload sizes, even though it's not required
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- No TX Event FIFOs
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- 2 Transmit buffers supporting up to 64 bytes of data payload
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'''
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self.MRAMConfiguration = TCAN4x5x_MRAM_Config()
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self.MRAMConfiguration = 0x0
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self.MRAMConfiguration.XIDNumElements = 1 # Extended ID number of elements, you MUST have a filter written to MRAM for each element defined
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self.MRAMConfiguration.SIDNumElements = 1 # Standard ID number of elements, you MUST have a filter written to MRAM for each element defined
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self.MRAMConfiguration.Rx0NumElements = 5 # RX0 Number of elements
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self.MRAMConfiguration.Rx0ElementSize = TCAN4x5x_MRAM_Element_Data_Size.MRAM_64_Byte_Data # RX0 data payload size
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self.MRAMConfiguration.Rx1NumElements = 0 # RX1 number of elements
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self.MRAMConfiguration.Rx1ElementSize = TCAN4x5x_MRAM_Element_Data_Size.MRAM_64_Byte_Data # RX1 data payload size
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self.MRAMConfiguration.RxBufNumElements = 0 # RX buffer number of elements
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self.MRAMConfiguration.RxBufElementSize = TCAN4x5x_MRAM_Element_Data_Size.MRAM_64_Byte_Data # RX buffer data payload size
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self.MRAMConfiguration.TxEventFIFONumElements = 0 # TX Event FIFO number of elements
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self.MRAMConfiguration.TxBufferNumElements = 2 # TX buffer number of elements
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self.MRAMConfiguration.TxBufferElementSize = TCAN4x5x_MRAM_Element_Data_Size.MRAM_64_Byte_Data # TX buffer data payload size
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def TCAN4x5x_Device_ClearInterrupts(self, ir):
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pass
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def TCAN_clearSPIerr(self) -> None:
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def TCAN_clearSPIerr(self) -> None:
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pass
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pass
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def TCAN_configure_interrupt_enable(self, ie) -> bool:
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def TCAN_configure_interrupt_enable(self, ie) -> bool:
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return True
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return True
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def TCAN_read_interrupts(self, ir) -> bool:
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def TCAN_read_interrupts(self, ir) -> bool:
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return True
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return True
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def TCAN_write_32(self, address, data) -> None:
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def TCAN_write_32(self, address, data) -> None:
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pass
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pass
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def TCAN_write(self, data, address, no_words) -> None:
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def TCAN_write(self, data, address, no_words) -> None:
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pass
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pass
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def TCAN_read_32(self, address, data) -> uint32_t:
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def TCAN_read_32(self, address, data) -> uint32_t:
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return 0
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return 0
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def TCAN_read(self,address, data, no_words) -> uint32_t:
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def TCAN_read(self, address, data, no_words) -> uint32_t:
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return 0
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return 0
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class TCAN4x5x_GFC_NO_MATCH_BEHAVIOR(Enum): # No Comments provided in original file
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class TCAN4x5x_GFC_NO_MATCH_BEHAVIOR(Enum): #No Comments provided in original file
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TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 = 0,
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TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 = 0,
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TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 = 1,
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TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 = 1,
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TCAN4x5x_GFC_REJECT = 2
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TCAN4x5x_GFC_REJECT = 2
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class TCAN4x5x_MRAM_Element_Data_Size(Enum):
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class TCAN4x5x_MRAM_Element_Data_Size(Enum):
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# 8 bytes of data payload
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# 8 bytes of data payload
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MRAM_8_Byte_Data = 0,
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MRAM_8_Byte_Data = 0,
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@ -103,642 +140,655 @@ class TCAN4x5x_MRAM_Element_Data_Size(Enum):
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# 64 bytes of data payload
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# 64 bytes of data payload
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MRAM_64_Byte_Data = 0x7
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MRAM_64_Byte_Data = 0x7
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class TCAN4x5x_MCAN_Data_Timing_Simple(ctypes.Structure):
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class TCAN4x5x_MCAN_Data_Timing_Simple(ctypes.Structure):
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_fields_ = [
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_fields_ = [
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# Prescaler value, interpreted as 1:x
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# Prescaler value, interpreted as 1:x
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# Valid range is: 1 to 32
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# Valid range is: 1 to 32
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("DataBitRatePrescaler", uint8_t, 6),
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("DataBitRatePrescaler", uint8_t, 6),
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# DTQBSP: Number of time quanta before sample point
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# DTQBSP: Number of time quanta before sample point
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# Valid values are: 2 to 33
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# Valid values are: 2 to 33
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("DataTqBeforeSamplePoint", uint8_t, 6),
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("DataTqBeforeSamplePoint", uint8_t, 6),
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# DTQASP: Number of time quanta after sample point
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# DTQASP: Number of time quanta after sample point
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# Valid values are: 1 to 16
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# Valid values are: 1 to 16
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("DataTqAfterSamplePoint", uint8_t, 5)
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("DataTqAfterSamplePoint", uint8_t, 5)
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]
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]
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class TCAN4x5x_MCAN_Data_Timing_Raw(ctypes.Structure):
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class TCAN4x5x_MCAN_Data_Timing_Raw(ctypes.Structure):
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_fields_= [
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_fields_ = [
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# DBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field + 1
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# DBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field + 1
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# Valid range is: 0 to 31
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# Valid range is: 0 to 31
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("DataBitRatePrescaler", uint8_t, 5),
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("DataBitRatePrescaler", uint8_t, 5),
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# DTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value in this field + 1
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# DTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value in this field + 1
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# Valid values are: 0 to 31
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# Valid values are: 0 to 31
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("DataTimeSeg1andProp", uint8_t, 5),
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("DataTimeSeg1andProp", uint8_t, 5),
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# DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1
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# DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 15
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# Valid values are: 0 to 15
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("DataTimeSeg2", uint8_t, 4),
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("DataTimeSeg2", uint8_t, 4),
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# DSJW: Data Resynchronization jump width. Interpreted by MCAN as the value is this field + 1
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# DSJW: Data Resynchronization jump width. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 15
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# Valid values are: 0 to 15
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("DataSyncJumpWidth", uint8_t, 4),
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("DataSyncJumpWidth", uint8_t, 4),
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# TDCO: Transmitter delay compensation offset
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# TDCO: Transmitter delay compensation offset
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# Valid values are 0 to 127 mtq
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# Valid values are 0 to 127 mtq
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("TDCOffset", uint8_t, 7),
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("TDCOffset", uint8_t, 7),
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# TDCFilter: Transmitter delay compensation Filter Window Length
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# TDCFilter: Transmitter delay compensation Filter Window Length
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# Valid values are 0 to 127 mtq
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# Valid values are 0 to 127 mtq
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("TDCFilter", uint8_t, 7)
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("TDCFilter", uint8_t, 7)
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]
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]
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class TCAN4x5x_MCAN_Nominal_Timing_Simple(ctypes.Structure):
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class TCAN4x5x_MCAN_Nominal_Timing_Simple(ctypes.Structure):
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_fields_ = [
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_fields_ = [
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# NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x
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# NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x
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# Valid range is: 1 to 512
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# Valid range is: 1 to 512
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("NominalBitRatePrescaler", uint16_t, 10),
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("NominalBitRatePrescaler", uint16_t, 10),
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# NTQBSP: The total number of time quanta prior to sample point
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# NTQBSP: The total number of time quanta prior to sample point
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# Valid values are: 2 to 257
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# Valid values are: 2 to 257
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("NominalTqBeforeSamplePoint", uint16_t, 9),
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("NominalTqBeforeSamplePoint", uint16_t, 9),
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# NTQASP: The total number of time quanta after the sample point
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# NTQASP: The total number of time quanta after the sample point
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# Valid values are: 2 to 128
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# Valid values are: 2 to 128
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("NominalTqAfterSamplePoint", uint8_t, 8)
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("NominalTqAfterSamplePoint", uint8_t, 8)
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]
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]
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class TCAN4x5x_MCAN_Nominal_Timing_Raw(ctypes.Structure):
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class TCAN4x5x_MCAN_Nominal_Timing_Raw(ctypes.Structure):
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_fields_ = [
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_fields_ = [
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# NBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field + 1
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# NBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field + 1
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# Valid range is: 0 to 511
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# Valid range is: 0 to 511
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("NominalBitRatePrescaler", uint16_t, 9),
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("NominalBitRatePrescaler", uint16_t, 9),
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# NTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value is this field + 1
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# NTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 255
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# Valid values are: 0 to 255
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("NominalTimeSeg1andProp", uint8_t, 8),
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("NominalTimeSeg1andProp", uint8_t, 8),
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# NTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1
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# NTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 127
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# Valid values are: 0 to 127
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("NominalTimeSeg2", uint8_t, 7),
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("NominalTimeSeg2", uint8_t, 7),
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# NSJW: Nominal time Resynchronization jump width. Interpreted by MCAN as the value is this field + 1
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# NSJW: Nominal time Resynchronization jump width. Interpreted by MCAN as the value is this field + 1
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# Valid values are: 0 to 127
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# Valid values are: 0 to 127
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("NominalSyncJumpWidth", uint8_t, 7)
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("NominalSyncJumpWidth", uint8_t, 7)
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]
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]
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class TCAN4x5x_MRAM_Config(ctypes.Structure):
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class TCAN4x5x_MRAM_Config(ctypes.Structure):
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_fields_ = [
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_fields_ = [
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# ************************
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# ************************
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# Filter Elements *
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# Filter Elements *
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# ************************
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# ************************
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# Standard ID Number of Filter Elements: The number of 11-bit filters the user would like
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# Standard ID Number of Filter Elements: The number of 11-bit filters the user would like
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# Valid range is: 0 to 128
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# Valid range is: 0 to 128
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("SIDNumElements", uint8_t, 8),
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("SIDNumElements", uint8_t, 8),
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# Extended ID Number of Filter Elements: The number of 29-bit filters the user would like
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# Extended ID Number of Filter Elements: The number of 29-bit filters the user would like
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# Valid range is: 0 to 64
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# Valid range is: 0 to 64
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("XIDNumElements", uint8_t, 7),
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("XIDNumElements", uint8_t, 7),
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# /************************
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# /************************
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# RX FIFO Elements *
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# RX FIFO Elements *
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# ************************/
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# ************************/
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# RX FIFO 0 number of elements: The number of elements for the RX FIFO 0
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# RX FIFO 0 number of elements: The number of elements for the RX FIFO 0
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# Valid range is: 0 to 64
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# Valid range is: 0 to 64
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("Rx0NumElements", uint8_t, 7),
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("Rx0NumElements", uint8_t, 7),
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# RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
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# RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
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("Rx0ElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
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("Rx0ElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
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# RX FIFO 1 number of elements: The number of elements for the RX FIFO 1
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# RX FIFO 1 number of elements: The number of elements for the RX FIFO 1
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# Valid range is: 0 to 64
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# Valid range is: 0 to 64
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("Rx1NumElements", uint8_t, 7),
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("Rx1NumElements", uint8_t, 7),
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# RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
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# RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
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("Rx1ElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
|
("Rx1ElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
|
||||||
|
|
||||||
# RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO)
|
# RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO)
|
||||||
# Valid range is: 0 to 64
|
# Valid range is: 0 to 64
|
||||||
("RxBufNumElements", uint8_t, 7),
|
("RxBufNumElements", uint8_t, 7),
|
||||||
|
|
||||||
# RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO
|
# RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO
|
||||||
("RxBufElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
|
("RxBufElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3),
|
||||||
|
|
||||||
# /************************
|
# /************************
|
||||||
#TX Buffer Elements *
|
# TX Buffer Elements *
|
||||||
# ************************/
|
# ************************/
|
||||||
|
|
||||||
# TX Event FIFO number of elements: The number of elements for the TX Event FIFO
|
# TX Event FIFO number of elements: The number of elements for the TX Event FIFO
|
||||||
# Valid range is: 0 to 32
|
# Valid range is: 0 to 32
|
||||||
("TxEventFIFONumElements", uint8_t, 6),
|
("TxEventFIFONumElements", uint8_t, 6),
|
||||||
|
|
||||||
# TX Buffers number of elements: The number of elements for the TX Buffers
|
# TX Buffers number of elements: The number of elements for the TX Buffers
|
||||||
# Valid range is: 0 to 32
|
# Valid range is: 0 to 32
|
||||||
("TxBufferNumElements", uint8_t, 6),
|
("TxBufferNumElements", uint8_t, 6),
|
||||||
|
|
||||||
# TX Buffers element size: The number of bytes for the TX Buffers (data payload)
|
# TX Buffers element size: The number of bytes for the TX Buffers (data payload)
|
||||||
("TxBufferElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3)
|
("TxBufferElementSize", TCAN4x5x_MRAM_Element_Data_Size, 3)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_Interrupt_Enable_bits(ctypes.Structure):
|
class TCAN4x5x_MCAN_Interrupt_Enable_bits(ctypes.Structure):
|
||||||
_fields_ = [
|
_fields_ = [
|
||||||
# IE[0] RF0NE: Rx FIFO 0 new message
|
# IE[0] RF0NE: Rx FIFO 0 new message
|
||||||
("RF0NE", uint8_t, 1),
|
("RF0NE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[1] RF0WE: Rx FIFO 0 watermark reached
|
# IE[1] RF0WE: Rx FIFO 0 watermark reached
|
||||||
("RF0WE", uint8_t, 1),
|
("RF0WE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[2] RF0FE: Rx FIFO 0 full
|
# IE[2] RF0FE: Rx FIFO 0 full
|
||||||
("RF0FE", uint8_t, 1),
|
("RF0FE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[3] RF0LE: Rx FIFO 0 message lost
|
# IE[3] RF0LE: Rx FIFO 0 message lost
|
||||||
("RF0LE", uint8_t, 1),
|
("RF0LE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[4] RF1NE: Rx FIFO 1 new message
|
# IE[4] RF1NE: Rx FIFO 1 new message
|
||||||
("RF1NE", uint8_t, 1),
|
("RF1NE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[5] RF1WE: RX FIFO 1 watermark reached
|
# IE[5] RF1WE: RX FIFO 1 watermark reached
|
||||||
("RF1WE", uint8_t, 1),
|
("RF1WE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[6] RF1FE: Rx FIFO 1 full
|
# IE[6] RF1FE: Rx FIFO 1 full
|
||||||
("RF1FE", uint8_t, 1),
|
("RF1FE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[7] RF1LE: Rx FIFO 1 message lost
|
# IE[7] RF1LE: Rx FIFO 1 message lost
|
||||||
("RF1LE", uint8_t, 1),
|
("RF1LE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[8] HPME: High priority message
|
# IE[8] HPME: High priority message
|
||||||
("HPME", uint8_t, 1),
|
("HPME", uint8_t, 1),
|
||||||
|
|
||||||
# IE[9] TCE: Transmission completed
|
# IE[9] TCE: Transmission completed
|
||||||
("TCE", uint8_t, 1),
|
("TCE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[10] TCFE: Transmission cancellation finished
|
# IE[10] TCFE: Transmission cancellation finished
|
||||||
("TCFE", uint8_t, 1),
|
("TCFE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[11] TFEE: Tx FIFO Empty
|
# IE[11] TFEE: Tx FIFO Empty
|
||||||
("TFEE", uint8_t, 1),
|
("TFEE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[12] TEFNE: Tx Event FIFO new entry
|
# IE[12] TEFNE: Tx Event FIFO new entry
|
||||||
("TEFNE", uint8_t, 1),
|
("TEFNE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[13] TEFWE: Tx Event FIFO watermark reached
|
# IE[13] TEFWE: Tx Event FIFO watermark reached
|
||||||
("TEFWE", uint8_t, 1),
|
("TEFWE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[14] TEFFE: Tx Event FIFO full
|
# IE[14] TEFFE: Tx Event FIFO full
|
||||||
("TEFFE", uint8_t, 1),
|
("TEFFE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[15] TEFLE: Tx Event FIFO element lost
|
# IE[15] TEFLE: Tx Event FIFO element lost
|
||||||
("TEFLE", uint8_t, 1),
|
("TEFLE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[16] TSWE: Timestamp wraparound
|
# IE[16] TSWE: Timestamp wraparound
|
||||||
("TSWE", uint8_t, 1),
|
("TSWE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[17] MRAFE: Message RAM access failure
|
# IE[17] MRAFE: Message RAM access failure
|
||||||
("MRAFE", uint8_t, 1),
|
("MRAFE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[18] TOOE: Time out occured
|
# IE[18] TOOE: Time out occured
|
||||||
("TOOE", uint8_t, 1),
|
("TOOE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[19] DRXE: Message stored to dedicated RX buffer
|
# IE[19] DRXE: Message stored to dedicated RX buffer
|
||||||
("DRXE", uint8_t, 1),
|
("DRXE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[20] BECE: MRAM Bit error corrected
|
# IE[20] BECE: MRAM Bit error corrected
|
||||||
("BECE", uint8_t, 1),
|
("BECE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[21] BEUE: MRAM Bit error uncorrected
|
# IE[21] BEUE: MRAM Bit error uncorrected
|
||||||
("BEUE", uint8_t, 1),
|
("BEUE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[22] ELOE: Error logging overflow
|
# IE[22] ELOE: Error logging overflow
|
||||||
("ELOE", uint8_t, 1),
|
("ELOE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[23] EPE: Error_passive status changed
|
# IE[23] EPE: Error_passive status changed
|
||||||
("EPE", uint8_t, 1),
|
("EPE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[24] EWE: Error_warning status changed
|
# IE[24] EWE: Error_warning status changed
|
||||||
("EWE", uint8_t, 1),
|
("EWE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[25] BOE: Bus_off status changed
|
# IE[25] BOE: Bus_off status changed
|
||||||
("BOE", uint8_t, 1),
|
("BOE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[26] WDIE: MRAM Watchdog Interrupt
|
# IE[26] WDIE: MRAM Watchdog Interrupt
|
||||||
("WDIE", uint8_t, 1),
|
("WDIE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[27] PEAE Protocol Error in arbitration phase (nominal bit time used)
|
# IE[27] PEAE Protocol Error in arbitration phase (nominal bit time used)
|
||||||
("PEAE", uint8_t, 1),
|
("PEAE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[28] PEDE: Protocol error in data phase (data bit time is used)
|
# IE[28] PEDE: Protocol error in data phase (data bit time is used)
|
||||||
("PEDE", uint8_t, 1),
|
("PEDE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[29] ARAE: Access to reserved address
|
# IE[29] ARAE: Access to reserved address
|
||||||
("ARAE", uint8_t, 1),
|
("ARAE", uint8_t, 1),
|
||||||
|
|
||||||
# IE[30:31] Reserved, not writable
|
# IE[30:31] Reserved, not writable
|
||||||
("reserved", uint8_t, 2)
|
("reserved", uint8_t, 2)
|
||||||
]
|
]
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_Interrupt_Enable(ctypes.Union):
|
|
||||||
_fields_= [("b", TCAN4x5x_MCAN_Interrupt_Enable_bits),
|
class TCAN4x5x_MCAN_Interrupt_Enable(ctypes.Union):
|
||||||
("word", uint32_t)]
|
_fields_ = [("b", TCAN4x5x_MCAN_Interrupt_Enable_bits),
|
||||||
|
("word", uint32_t)]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_Interrupts_bits(ctypes.Structure):
|
class TCAN4x5x_MCAN_Interrupts_bits(ctypes.Structure):
|
||||||
_fields_ = [
|
_fields_ = [
|
||||||
# IR[0] RF0N: Rx FIFO 0 new message
|
# IR[0] RF0N: Rx FIFO 0 new message
|
||||||
("RF0N", uint8_t, 1),
|
("RF0N", uint8_t, 1),
|
||||||
|
|
||||||
# IR[1] RF0W: Rx FIFO 0 watermark reached
|
# IR[1] RF0W: Rx FIFO 0 watermark reached
|
||||||
("RF0W", uint8_t, 1),
|
("RF0W", uint8_t, 1),
|
||||||
|
|
||||||
# IR[2] RF0F: Rx FIFO 0 full
|
# IR[2] RF0F: Rx FIFO 0 full
|
||||||
("RF0F", uint8_t, 1),
|
("RF0F", uint8_t, 1),
|
||||||
|
|
||||||
# IR[3] RF0L: Rx FIFO 0 message lost
|
# IR[3] RF0L: Rx FIFO 0 message lost
|
||||||
("RF0L", uint8_t, 1),
|
("RF0L", uint8_t, 1),
|
||||||
|
|
||||||
# IR[4] RF1N: Rx FIFO 1 new message
|
# IR[4] RF1N: Rx FIFO 1 new message
|
||||||
("RF1N", uint8_t, 1),
|
("RF1N", uint8_t, 1),
|
||||||
|
|
||||||
# IR[5] RF1W: RX FIFO 1 watermark reached
|
# IR[5] RF1W: RX FIFO 1 watermark reached
|
||||||
("RF1W", uint8_t, 1),
|
("RF1W", uint8_t, 1),
|
||||||
|
|
||||||
# IR[6] RF1F: Rx FIFO 1 full
|
# IR[6] RF1F: Rx FIFO 1 full
|
||||||
("RF1F", uint8_t, 1),
|
("RF1F", uint8_t, 1),
|
||||||
|
|
||||||
# IR[7] RF1L: Rx FIFO 1 message lost
|
# IR[7] RF1L: Rx FIFO 1 message lost
|
||||||
("RF1L", uint8_t, 1),
|
("RF1L", uint8_t, 1),
|
||||||
|
|
||||||
# IR[8] HPM: High priority message
|
# IR[8] HPM: High priority message
|
||||||
("HPM", uint8_t, 1),
|
("HPM", uint8_t, 1),
|
||||||
|
|
||||||
# IR[9] TC: Transmission completed
|
# IR[9] TC: Transmission completed
|
||||||
("TC", uint8_t, 1),
|
("TC", uint8_t, 1),
|
||||||
|
|
||||||
# IR[10] TCF: Transmission cancellation finished
|
# IR[10] TCF: Transmission cancellation finished
|
||||||
("TCF", uint8_t, 1),
|
("TCF", uint8_t, 1),
|
||||||
|
|
||||||
# IR[11] TFE: Tx FIFO Empty
|
# IR[11] TFE: Tx FIFO Empty
|
||||||
("TFE", uint8_t, 1),
|
("TFE", uint8_t, 1),
|
||||||
|
|
||||||
# IR[12] TEFN: Tx Event FIFO new entry
|
# IR[12] TEFN: Tx Event FIFO new entry
|
||||||
("TEFN", uint8_t, 1),
|
("TEFN", uint8_t, 1),
|
||||||
|
|
||||||
# IR[13] TEFW: Tx Event FIFO water mark reached
|
# IR[13] TEFW: Tx Event FIFO water mark reached
|
||||||
("TEFW", uint8_t, 1),
|
("TEFW", uint8_t, 1),
|
||||||
|
|
||||||
# IR[14] TEFF: Tx Event FIFO full
|
# IR[14] TEFF: Tx Event FIFO full
|
||||||
("TEFF", uint8_t, 1),
|
("TEFF", uint8_t, 1),
|
||||||
|
|
||||||
# IR[15] TEFL: Tx Event FIFO element lost
|
# IR[15] TEFL: Tx Event FIFO element lost
|
||||||
("TEFL", uint8_t, 1),
|
("TEFL", uint8_t, 1),
|
||||||
|
|
||||||
# IR[16] TSW: Timestamp wrapped around
|
# IR[16] TSW: Timestamp wrapped around
|
||||||
("TSW", uint8_t, 1),
|
("TSW", uint8_t, 1),
|
||||||
|
|
||||||
# IR[17] MRAF: Message RAM access failure
|
# IR[17] MRAF: Message RAM access failure
|
||||||
("MRAF", uint8_t, 1),
|
("MRAF", uint8_t, 1),
|
||||||
|
|
||||||
# IR[18] TOO: Time out occurred
|
# IR[18] TOO: Time out occurred
|
||||||
("TOO", uint8_t, 1),
|
("TOO", uint8_t, 1),
|
||||||
|
|
||||||
# IR[19] DRX: Message stored to dedicated RX buffer
|
# IR[19] DRX: Message stored to dedicated RX buffer
|
||||||
("DRX", uint8_t, 1),
|
("DRX", uint8_t, 1),
|
||||||
|
|
||||||
# IR[20] BEC: MRAM Bit error corrected
|
# IR[20] BEC: MRAM Bit error corrected
|
||||||
("BEC", uint8_t, 1),
|
("BEC", uint8_t, 1),
|
||||||
|
|
||||||
# IR[21] BEU: MRAM Bit error uncorrected
|
# IR[21] BEU: MRAM Bit error uncorrected
|
||||||
("BEU", uint8_t, 1),
|
("BEU", uint8_t, 1),
|
||||||
|
|
||||||
# IR[22] ELO: Error logging overflow
|
# IR[22] ELO: Error logging overflow
|
||||||
("ELO", uint8_t, 1),
|
("ELO", uint8_t, 1),
|
||||||
|
|
||||||
# IR[23] EP: Error_passive status changed
|
# IR[23] EP: Error_passive status changed
|
||||||
("EP", uint8_t, 1),
|
("EP", uint8_t, 1),
|
||||||
|
|
||||||
# IR[24] EW: Error_warning status changed
|
# IR[24] EW: Error_warning status changed
|
||||||
("EW", uint8_t, 1),
|
("EW", uint8_t, 1),
|
||||||
|
|
||||||
# IR[25] BO: Bus_off status changed
|
# IR[25] BO: Bus_off status changed
|
||||||
("BO", uint8_t, 1),
|
("BO", uint8_t, 1),
|
||||||
|
|
||||||
# IR[26] WDI: MRAM Watchdog Interrupt
|
# IR[26] WDI: MRAM Watchdog Interrupt
|
||||||
("WDI", uint8_t, 1),
|
("WDI", uint8_t, 1),
|
||||||
|
|
||||||
# IR[27] PEA Protocol Error in arbitration phase (nominal bit time used)
|
# IR[27] PEA Protocol Error in arbitration phase (nominal bit time used)
|
||||||
("PEA", uint8_t, 1),
|
("PEA", uint8_t, 1),
|
||||||
|
|
||||||
# IR[28] PED: Protocol error in data phase (data bit time is used)
|
# IR[28] PED: Protocol error in data phase (data bit time is used)
|
||||||
("PED", uint8_t, 1),
|
("PED", uint8_t, 1),
|
||||||
|
|
||||||
# IR[29] ARA: Access to reserved address
|
# IR[29] ARA: Access to reserved address
|
||||||
("ARA", uint8_t, 1),
|
("ARA", uint8_t, 1),
|
||||||
|
|
||||||
# IR[30:31] Reserved, not writable
|
# IR[30:31] Reserved, not writable
|
||||||
("reserved", uint8_t, 1)
|
("reserved", uint8_t, 1)
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_Interrupts(ctypes.Union):
|
class TCAN4x5x_MCAN_Interrupts(ctypes.Union):
|
||||||
_fields_ = [("b", TCAN4x5x_MCAN_Interrupts_bits),
|
_fields_ = [("b", TCAN4x5x_MCAN_Interrupts_bits),
|
||||||
("words", uint32_t)]
|
("words", uint32_t)]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_RX_Header(ctypes.Structure):
|
class TCAN4x5x_MCAN_RX_Header(ctypes.Structure):
|
||||||
_fields_ = [
|
_fields_ = [
|
||||||
# CAN ID received
|
# CAN ID received
|
||||||
("ID", uint32_t, 29),
|
("ID", uint32_t, 29),
|
||||||
|
|
||||||
# Remote Transmission Request flag
|
# Remote Transmission Request flag
|
||||||
("RTR", uint8_t, 1),
|
("RTR", uint8_t, 1),
|
||||||
|
|
||||||
# Extended Identifier flag
|
# Extended Identifier flag
|
||||||
("XTD", uint8_t, 1),
|
("XTD", uint8_t, 1),
|
||||||
|
|
||||||
# Error state indicator flag
|
# Error state indicator flag
|
||||||
("ESI", uint8_t, 1),
|
("ESI", uint8_t, 1),
|
||||||
|
|
||||||
# Receive time stamp
|
# Receive time stamp
|
||||||
("RXTS", uint16_t, 16),
|
("RXTS", uint16_t, 16),
|
||||||
|
|
||||||
# Data length code
|
# Data length code
|
||||||
("DLC", uint8_t, 4),
|
("DLC", uint8_t, 4),
|
||||||
|
|
||||||
# Bit rate switch used flag
|
# Bit rate switch used flag
|
||||||
("BRS", uint8_t, 1),
|
("BRS", uint8_t, 1),
|
||||||
|
|
||||||
# CAN FD Format flag
|
# CAN FD Format flag
|
||||||
("FDF", uint8_t, 1),
|
("FDF", uint8_t, 1),
|
||||||
|
|
||||||
# Reserved (0)
|
# Reserved (0)
|
||||||
("reserved", uint8_t, 2),
|
("reserved", uint8_t, 2),
|
||||||
|
|
||||||
# Filter index that this message matched
|
# Filter index that this message matched
|
||||||
("FIDX", uint8_t, 7),
|
("FIDX", uint8_t, 7),
|
||||||
|
|
||||||
# Accepted non matching frame flag
|
# Accepted non matching frame flag
|
||||||
("ANMF", uint8_t, 1)
|
("ANMF", uint8_t, 1)
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_Device_Interrupts_bits(ctypes.Structure):
|
class TCAN4x5x_Device_Interrupts_bits(ctypes.Structure):
|
||||||
_fields_ = {
|
_fields_ = {
|
||||||
# DEV_IR[0] VTWD: Global Voltage, Temp, or Watchdog (if equipped) Interrupt
|
# DEV_IR[0] VTWD: Global Voltage, Temp, or Watchdog (if equipped) Interrupt
|
||||||
("VTWD", uint8_t, 1),
|
("VTWD", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[1] M_CAN_INT: There are MCAN interrupts pending
|
# DEV_IR[1] M_CAN_INT: There are MCAN interrupts pending
|
||||||
("M_CAN_INT", uint8_t, 1),
|
("M_CAN_INT", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[2] : Selective Wake Error (If equipped)
|
# DEV_IR[2] : Selective Wake Error (If equipped)
|
||||||
("SWERR", uint8_t, 1),
|
("SWERR", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[3] : SPI Error
|
# DEV_IR[3] : SPI Error
|
||||||
("SPIERR", uint8_t, 1),
|
("SPIERR", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[4] : CBF, CAN Bus Fault
|
# DEV_IR[4] : CBF, CAN Bus Fault
|
||||||
("CBF", uint8_t, 1),
|
("CBF", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[5] : CANERR, CAN Error
|
# DEV_IR[5] : CANERR, CAN Error
|
||||||
("CANERR", uint8_t, 1),
|
("CANERR", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[6] : WKRQ, Wake Request
|
# DEV_IR[6] : WKRQ, Wake Request
|
||||||
("WKRQ", uint8_t, 1),
|
("WKRQ", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[7] : GLOBALERR, Global Error. Is the OR output of all interrupts
|
# DEV_IR[7] : GLOBALERR, Global Error. Is the OR output of all interrupts
|
||||||
("GLOBALERR", uint8_t, 1),
|
("GLOBALERR", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[8] : CANDOM, Can bus stuck dominant
|
# DEV_IR[8] : CANDOM, Can bus stuck dominant
|
||||||
("CANDOM", uint8_t, 1),
|
("CANDOM", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[9] : RESERVED
|
# DEV_IR[9] : RESERVED
|
||||||
("RESERVED", uint8_t, 1),
|
("RESERVED", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[10] : CANTO, CAN Timeout
|
# DEV_IR[10] : CANTO, CAN Timeout
|
||||||
("CANTO", uint8_t, 1),
|
("CANTO", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[11] : RESERVED
|
# DEV_IR[11] : RESERVED
|
||||||
("RESERVED2", uint8_t, 1),
|
("RESERVED2", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
|
# DEV_IR[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
|
||||||
("FRAME_OVF", uint8_t, 1),
|
("FRAME_OVF", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[13] : WKERR, Wake Error
|
# DEV_IR[13] : WKERR, Wake Error
|
||||||
("WKERR", uint8_t, 1),
|
("WKERR", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[14] : LWU, Local Wake Up
|
# DEV_IR[14] : LWU, Local Wake Up
|
||||||
("LWU", uint8_t, 1),
|
("LWU", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[15] : CANINT, CAN Bus Wake Up Interrupt
|
# DEV_IR[15] : CANINT, CAN Bus Wake Up Interrupt
|
||||||
("CANINT", uint8_t, 1),
|
("CANINT", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[16] : ECCERR, MRAM ECC Error
|
# DEV_IR[16] : ECCERR, MRAM ECC Error
|
||||||
("ECCERR", uint8_t, 1),
|
("ECCERR", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[17] : Reserved
|
# DEV_IR[17] : Reserved
|
||||||
("RESERVED3", uint8_t, 1),
|
("RESERVED3", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[18] : WDTO, Watchdog Time Out
|
# DEV_IR[18] : WDTO, Watchdog Time Out
|
||||||
("WDTO", uint8_t, 1),
|
("WDTO", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[19] : TSD, Thermal Shut Down
|
# DEV_IR[19] : TSD, Thermal Shut Down
|
||||||
("TSD", uint8_t, 1),
|
("TSD", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[20] : PWRON, Power On Interrupt
|
# DEV_IR[20] : PWRON, Power On Interrupt
|
||||||
("PWRON", uint8_t, 1),
|
("PWRON", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[21] : UVIO, Undervoltage on UVIO
|
# DEV_IR[21] : UVIO, Undervoltage on UVIO
|
||||||
("UVIO", uint8_t, 1),
|
("UVIO", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[22] : UVSUP, Undervoltage on VSUP and VCCOUT
|
# DEV_IR[22] : UVSUP, Undervoltage on VSUP and VCCOUT
|
||||||
("UVSUP", uint8_t, 1),
|
("UVSUP", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults
|
# DEV_IR[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults
|
||||||
("SMS", uint8_t, 1),
|
("SMS", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[24] : CANBUSBAT, CAN Shorted to VBAT
|
# DEV_IR[24] : CANBUSBAT, CAN Shorted to VBAT
|
||||||
("CANBUSBAT", uint8_t, 1),
|
("CANBUSBAT", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[25] : CANBUSGND, CAN Shorted to GND
|
# DEV_IR[25] : CANBUSGND, CAN Shorted to GND
|
||||||
("CANBUSGND", uint8_t, 1),
|
("CANBUSGND", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[26] : CANBUSOPEN, CAN Open fault
|
# DEV_IR[26] : CANBUSOPEN, CAN Open fault
|
||||||
("CANBUSOPEN", uint8_t, 1),
|
("CANBUSOPEN", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[27] : CANLGND, CANL GND
|
# DEV_IR[27] : CANLGND, CANL GND
|
||||||
("CANLGND", uint8_t, 1),
|
("CANLGND", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[28] : CANHBAT, CANH to VBAT
|
# DEV_IR[28] : CANHBAT, CANH to VBAT
|
||||||
("CANHBAT", uint8_t, 1),
|
("CANHBAT", uint8_t, 1),
|
||||||
|
|
||||||
# DEV_IR[29] : CANHCANL, CANH and CANL shorted
|
# DEV_IR[29] : CANHCANL, CANH and CANL shorted
|
||||||
("CANHCANL", uint8_t, 1)
|
("CANHCANL", uint8_t, 1)
|
||||||
|
|
||||||
# DEV_IR[30] : CANBUSTERMOPEN, CAN Bus has termination point open
|
# DEV_IR[30] : CANBUSTERMOPEN, CAN Bus has termination point open
|
||||||
("CANBUSTERMOPEN", uint8_t, 1)
|
("CANBUSTERMOPEN", uint8_t, 1)
|
||||||
|
|
||||||
# DEV_IR[31] : CANBUSNOM, CAN Bus is normal flag
|
# DEV_IR[31] : CANBUSNOM, CAN Bus is normal flag
|
||||||
("CANBUSNORM", uint8_t, 1)
|
("CANBUSNORM", uint8_t, 1)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_Device_Interrupts(ctypes.Union):
|
class TCAN4x5x_Device_Interrupts(ctypes.Union):
|
||||||
_fields_ = [("b", TCAN4x5x_Device_Interrupts_bits),
|
_fields_ = [("b", TCAN4x5x_Device_Interrupts_bits),
|
||||||
("word", uint32_t)]
|
("word", uint32_t)]
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_CCCR_Config_bits(ctypes.Structure):
|
class TCAN4x5x_MCAN_CCCR_Config_bits(ctypes.Structure):
|
||||||
_fields_ = [
|
_fields_ = [
|
||||||
# Reserved (0)
|
# Reserved (0)
|
||||||
("reserved", uint8_t, 2),
|
("reserved", uint8_t, 2),
|
||||||
|
|
||||||
# ASM: Restricted Operation Mode. The device can only listen to CAN traffic and acknowledge, but not send anything.
|
# ASM: Restricted Operation Mode. The device can only listen to CAN traffic and acknowledge, but not send anything.
|
||||||
("ASM", uint8_t, 1),
|
("ASM", uint8_t, 1),
|
||||||
|
|
||||||
# Reserved (0)
|
# Reserved (0)
|
||||||
("reserved2", uint8_t, 1),
|
("reserved2", uint8_t, 1),
|
||||||
|
|
||||||
# CSR: Clock stop request
|
# CSR: Clock stop request
|
||||||
("CSR", uint8_t, 1),
|
("CSR", uint8_t, 1),
|
||||||
|
|
||||||
# MON: Bus monitoring mode. The device may only listen to CAN traffic, and is not allowed to acknowledge or send error frames.
|
# MON: Bus monitoring mode. The device may only listen to CAN traffic, and is not allowed to acknowledge or send error frames.
|
||||||
("MON", uint8_t, 1),
|
("MON", uint8_t, 1),
|
||||||
|
|
||||||
# DAR: Disable automatic retransmission. If a transmission errors, gets a NACK, or loses arbitration, the MCAN controller will NOT try to transmit again
|
# DAR: Disable automatic retransmission. If a transmission errors, gets a NACK, or loses arbitration, the MCAN controller will NOT try to transmit again
|
||||||
("DAR", uint8_t, 1),
|
("DAR", uint8_t, 1),
|
||||||
|
|
||||||
# TEST: MCAN Test mode enable
|
# TEST: MCAN Test mode enable
|
||||||
("TEST", uint8_t, 1),
|
("TEST", uint8_t, 1),
|
||||||
|
|
||||||
# FDOE: Can FD mode enabled, master enable for CAN FD support
|
# FDOE: Can FD mode enabled, master enable for CAN FD support
|
||||||
("FDOE", uint8_t, 1),
|
("FDOE", uint8_t, 1),
|
||||||
|
|
||||||
# BRSE: Bit rate switch enabled for can FD. Master enable for bit rate switching support
|
# BRSE: Bit rate switch enabled for can FD. Master enable for bit rate switching support
|
||||||
("BRSE", uint8_t, 1),
|
("BRSE", uint8_t, 1),
|
||||||
|
|
||||||
# Reserved (0)
|
# Reserved (0)
|
||||||
("reserved3", uint8_t, 1),
|
("reserved3", uint8_t, 1),
|
||||||
|
|
||||||
# PXHD: Protocol exception handling disable
|
# PXHD: Protocol exception handling disable
|
||||||
# 0 = Protocol exception handling enabled [default]
|
# 0 = Protocol exception handling enabled [default]
|
||||||
# 1 = protocol exception handling disabled
|
# 1 = protocol exception handling disabled
|
||||||
("PXHD", uint8_t, 1),
|
("PXHD", uint8_t, 1),
|
||||||
|
|
||||||
# EFBI: Edge filtering during bus integration. 0 Disables this [default]
|
# EFBI: Edge filtering during bus integration. 0 Disables this [default]
|
||||||
("EFBI", uint8_t, 1),
|
("EFBI", uint8_t, 1),
|
||||||
|
|
||||||
# TXP: Transmit Pause Enable: Pause for 2 can bit times before next transmission
|
# TXP: Transmit Pause Enable: Pause for 2 can bit times before next transmission
|
||||||
("TXP", uint8_t, 1),
|
("TXP", uint8_t, 1),
|
||||||
|
|
||||||
# NSIO: Non Iso Operation
|
# NSIO: Non Iso Operation
|
||||||
# 0: CAN FD frame format according to ISO 11898-1:2015 [default]
|
# 0: CAN FD frame format according to ISO 11898-1:2015 [default]
|
||||||
# 1: CAN FD frame format according to Bosch CAN FD Spec v1
|
# 1: CAN FD frame format according to Bosch CAN FD Spec v1
|
||||||
("NISO", uint8_t, 1)
|
("NISO", uint8_t, 1)
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_CCCR_Config(ctypes.Union):
|
class TCAN4x5x_MCAN_CCCR_Config(ctypes.Union):
|
||||||
_fields_ = [("b", TCAN4x5x_MCAN_CCCR_Config_bits),
|
_fields_ = [("b", TCAN4x5x_MCAN_CCCR_Config_bits),
|
||||||
("word", uint32_t)]
|
("word", uint32_t)]
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_Global_Filter_Configuration_bits(ctypes.Structure):
|
class TCAN4x5x_MCAN_Global_Filter_Configuration_bits(ctypes.Structure):
|
||||||
_fields_ = [
|
_fields_ = [
|
||||||
# GFC[0] : Reject Remote Frames for Extended IDs
|
# GFC[0] : Reject Remote Frames for Extended IDs
|
||||||
("RRFE", uint8_t, 1)
|
("RRFE", uint8_t, 1)
|
||||||
|
|
||||||
# GFC[1] : Reject Remote Frames for Standard IDs
|
# GFC[1] : Reject Remote Frames for Standard IDs
|
||||||
("RRFS", uint8_t, 1),
|
("RRFS", uint8_t, 1),
|
||||||
|
|
||||||
# GFC[3:2] : Accept Non-matching Frames Extended
|
# GFC[3:2] : Accept Non-matching Frames Extended
|
||||||
# Valid values:
|
# Valid values:
|
||||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accept into RXFIFO0
|
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accept into RXFIFO0
|
||||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 : Accept into RXFIFO1
|
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 : Accept into RXFIFO1
|
||||||
# TCAN4x5x_GFC_REJECT : Reject
|
# TCAN4x5x_GFC_REJECT : Reject
|
||||||
("ANFE", TCAN4x5x_GFC_NO_MATCH_BEHAVIOR, 2),
|
("ANFE", TCAN4x5x_GFC_NO_MATCH_BEHAVIOR, 2),
|
||||||
|
|
||||||
# GFC[5:4] : Accept Non-matching Frames Standard
|
# GFC[5:4] : Accept Non-matching Frames Standard
|
||||||
# Valid values:
|
# Valid values:
|
||||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accept into RXFIFO0
|
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accept into RXFIFO0
|
||||||
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 : Accept into RXFIFO1
|
# TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO1 : Accept into RXFIFO1
|
||||||
# TCAN4x5x_GFC_REJECT : Reject
|
# TCAN4x5x_GFC_REJECT : Reject
|
||||||
("ANFS", TCAN4x5x_GFC_NO_MATCH_BEHAVIOR, 2),
|
("ANFS", TCAN4x5x_GFC_NO_MATCH_BEHAVIOR, 2),
|
||||||
|
|
||||||
# Reserved
|
# Reserved
|
||||||
("reserved", uint32_t, 26)
|
("reserved", uint32_t, 26)
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_MCAN_Global_Filter_Configuration(ctypes.Union):
|
class TCAN4x5x_MCAN_Global_Filter_Configuration(ctypes.Union):
|
||||||
_fields_ = [("b", TCAN4x5x_MCAN_Global_Filter_Configuration_bits),
|
_fields_ = [("b", TCAN4x5x_MCAN_Global_Filter_Configuration_bits),
|
||||||
("word", uint32_t)]
|
("word", uint32_t)]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_device_interrupt_enable_bits(ctypes.BigEndianStructure):
|
class TCAN4x5x_device_interrupt_enable_bits(ctypes.BigEndianStructure):
|
||||||
_fields_ = [
|
_fields_ = [
|
||||||
# @brief DEV_IE[0:7] : RESERVED
|
# @brief DEV_IE[0:7] : RESERVED
|
||||||
("RESERVED1", uint8_t , 8),
|
("RESERVED1", uint8_t, 8),
|
||||||
|
|
||||||
# @brief DEV_IE[8] : CANDOM, Can bus stuck dominant
|
# @brief DEV_IE[8] : CANDOM, Can bus stuck dominant
|
||||||
("CANDOMEN", uint8_t , 1),
|
("CANDOMEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[9] : RESERVED
|
# @brief DEV_IE[9] : RESERVED
|
||||||
("RESERVED2", uint8_t , 1),
|
("RESERVED2", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[10] : CANTO, CAN Timeout
|
# @brief DEV_IE[10] : CANTO, CAN Timeout
|
||||||
("CANTOEN", uint8_t , 1),
|
("CANTOEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[11] : RESERVED
|
# @brief DEV_IE[11] : RESERVED
|
||||||
("RESERVED3", uint8_t , 1),
|
("RESERVED3", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
|
# @brief DEV_IE[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
|
||||||
("FRAME_OVFEN", uint8_t , 1),
|
("FRAME_OVFEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[13] : WKERR, Wake Error
|
# @brief DEV_IE[13] : WKERR, Wake Error
|
||||||
("WKERREN", uint8_t , 1),
|
("WKERREN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[14] : LWU, Local Wake Up
|
# @brief DEV_IE[14] : LWU, Local Wake Up
|
||||||
("LWUEN", uint8_t , 1),
|
("LWUEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[15] : CANINT, CAN Bus Wake Up Interrupt
|
# @brief DEV_IE[15] : CANINT, CAN Bus Wake Up Interrupt
|
||||||
("CANINTEN", uint8_t , 1),
|
("CANINTEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[16] : ECCERR, MRAM ECC Error
|
# @brief DEV_IE[16] : ECCERR, MRAM ECC Error
|
||||||
("ECCERREN", uint8_t , 1),
|
("ECCERREN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[17] : Reserved
|
# @brief DEV_IE[17] : Reserved
|
||||||
("RESERVED4", uint8_t , 1),
|
("RESERVED4", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[18] : WDTO, Watchdog Time Out
|
# @brief DEV_IE[18] : WDTO, Watchdog Time Out
|
||||||
("WDTOEN", uint8_t , 1),
|
("WDTOEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[19] : TSD, Thermal Shut Down
|
# @brief DEV_IE[19] : TSD, Thermal Shut Down
|
||||||
("TSDEN", uint8_t , 1),
|
("TSDEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[20] : PWRON, Power On Interrupt
|
# @brief DEV_IE[20] : PWRON, Power On Interrupt
|
||||||
("PWRONEN", uint8_t , 1),
|
("PWRONEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[21] : UVIO, Undervoltage on UVIO
|
# @brief DEV_IE[21] : UVIO, Undervoltage on UVIO
|
||||||
("UVIOEN", uint8_t , 1),
|
("UVIOEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[22] : UVSUP, Undervoltage on VSUP and VCCOUT
|
# @brief DEV_IE[22] : UVSUP, Undervoltage on VSUP and VCCOUT
|
||||||
("UVSUPEN", uint8_t , 1),
|
("UVSUPEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults
|
# @brief DEV_IE[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults
|
||||||
("SMSEN", uint8_t , 1),
|
("SMSEN", uint8_t, 1),
|
||||||
|
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# @brief DEV_IE[24] : CANBUSBAT, CAN Shorted to VBAT
|
# @brief DEV_IE[24] : CANBUSBAT, CAN Shorted to VBAT
|
||||||
("CANBUSBATEN", uint8_t , 1),
|
("CANBUSBATEN", uint8_t, 1),
|
||||||
|
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# @brief DEV_IE[25] : CANBUSGND, CAN Shorted to GND
|
# @brief DEV_IE[25] : CANBUSGND, CAN Shorted to GND
|
||||||
("CANBUSGNDEN", uint8_t , 1),
|
("CANBUSGNDEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[26] : CANBUSOPEN, CAN Open fault
|
# @brief DEV_IE[26] : CANBUSOPEN, CAN Open fault
|
||||||
("CANBUSOPENEN", uint8_t , 1),
|
("CANBUSOPENEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[27] : CANLGND, CANL GND
|
# @brief DEV_IE[27] : CANLGND, CANL GND
|
||||||
("CANLGNDEN", uint8_t , 1),
|
("CANLGNDEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[28] : CANHBAT, CANH to VBAT
|
# @brief DEV_IE[28] : CANHBAT, CANH to VBAT
|
||||||
("CANHBATEN", uint8_t , 1),
|
("CANHBATEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[29] : CANHCANL, CANH and CANL shorted
|
# @brief DEV_IE[29] : CANHCANL, CANH and CANL shorted
|
||||||
("CANHCANLEN", uint8_t , 1),
|
("CANHCANLEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[30] : CANBUSTERMOPEN, CAN Bus has termination point open
|
# @brief DEV_IE[30] : CANBUSTERMOPEN, CAN Bus has termination point open
|
||||||
("CANBUSTERMOPENEN", uint8_t , 1),
|
("CANBUSTERMOPENEN", uint8_t, 1),
|
||||||
|
|
||||||
# @brief DEV_IE[31] : CANBUSNOM, CAN Bus is normal flag
|
# @brief DEV_IE[31] : CANBUSNOM, CAN Bus is normal flag
|
||||||
("CANBUSNORMEN", uint8_t , 1)
|
("CANBUSNORMEN", uint8_t, 1)
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class TCAN4x5x_device_interrupt_enable(ctypes.Union):
|
class TCAN4x5x_device_interrupt_enable(ctypes.Union):
|
||||||
_fields_ = [("b", TCAN4x5x_device_interrupt_enable_bits),
|
_fields_ = [("b", TCAN4x5x_device_interrupt_enable_bits),
|
||||||
("word", uint32_t)]
|
("word", uint32_t)]
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue